In semiconductor integrated circuits, it is desirable to use a power supply voltage that is as small as possible in order to reduce power consumption. Accordingly, reduction of the power supply voltage is promoted in the semiconductor integrated circuits. On the other hand, traditional integrated circuits using a high power supply voltage remain used. For this reason, plural types of power supply voltages must be sometimes prepared and switched for use in a same system. When connecting integrated circuits having different power supply voltages, it is necessary to convert a signal voltage using a level shift circuit.
A CMOS level shift circuit is known among such level shift circuits. In this case, a through-current constantly flows between PMOS and NMOS transistors in the CMOS level shift circuit with a simple structure, so that there is a problem that power consumption is large. Then, a CMOS level shift circuit that prevents a through-current flow is described in Patent Document 1.
FIG. 9 is a circuit diagram of the CMOS level shift circuit described in Patent Document 1. Referring to FIG. 9, N-type MOS transistors 14 and 15 are connected in series between a power supply voltage and ground. A signal supplied from an external input terminal 11 is transmitted to a gate of the N-type MOS transistor 15 through an inverter 12, and is also transmitted to a gate of the N-type MOS transistor 14 through the inverter 12 and an inverter 13. A HIGH-output positive feedback circuit formed of an inverter 17 and a P-type MOS transistor 16 is connected to respective drains of the N-type MOS transistors 14 and 15. The inverters 12 and 13 are inverters that operate on a low-voltage power supply.
The signal with a low voltage is supplied from the external input terminal 11 and a high-voltage signal obtained by level shifting the low-voltage signal is extracted from an external output terminal 18 in such a CMOS level shift circuit. In this case, the input signal is supplied to the N-type MOS transistor 14 through the inverters 12 and 13, and the input signal is supplied to the N-type MOS transistor 15 through the inverter 12. Thus, one of the N-type MOS transistors 14 and 15 constantly turns off. Accordingly, no through-current flows across the N-type MOS transistors 14 and 15 in a normal state.    Patent Document 1: JP Patent Kokai Publication No. JP-A-7-226670